The present disclosure relates generally to semiconductor devices and methods of manufacturing semiconductor devices, and more particularly to methods and devices for passivating gate dielectric films.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and designs have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of these advances, functional density has generally increased while geometry size has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
During the scaling trend, various materials have been implemented for a gate electrode and gate dielectric for MOS or CMOS devices. More specifically, high-k dielectric films have been employed for the gate dielectric to achieve the required equivalent oxide thickness (EOT) while keeping the leakage current of the device to a minimum. However, using high-K dielectric films for the gate dielectric may adversely affect a threshold voltage due to Fermi-level pinning phenomenon at the gate dielectric/electrode interface and thus, may lead to poor device performance and reliability.
Therefore, what is needed is a simple and cost-effective method and device for passivating a gate dielectric film in semiconductor devices.